Post Graduate Diploma in VLSI Design & Embedded Systems

Eligibility: BE, B.Tech, ME, M.Tech, MCA, BCA, MSc, BSc
Duration: 5 Months

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VLSI Design ensures that a fresher is prepared on the entire essential aspects of VLSI front end domain including training on VLSI flow, SOC design and verification concepts, digital design, Verilog, Systemverilog. . The VSLI design course content is well structured and mapped with leading industry requirements and their standards.

Outcomes

Lack of fundamentals in Advanced Digital Design, Analog Design and Verilog based design and verification becomes a major deterrent for fresher in finding right career opportunities. VLSI design course ensures that fresher is empowered with all the essential skill set required for various jobs in VLSI front end domain. The course is completely practical oriented with each aspect of course involving multiple hands on projects.

Part I - Embedded

  • Basic Electronics & Introduction to Embedded Concept
  • Programming in C & Advance C
  • Data Structures
  • ARM7 Architecture Programming in Embedded C & Embedded Protocols- UART, I2C, SPI, CORTEX-M Architecture
  • Linux Commands & Shell Scripting

Part II - VLSI Specialization

  • Advance Digital System Design
  • Verilog/VHDL Programming
  • FPGA Design – Advanced
  • HDL Synthesis
  • SystemVerilog
  • Functional Verification with UVM

Part I - Embedded

Basic Electronics & Embedded Concepts - 4 days

  • Analog Electronics : Semi Conductor devices and circuits
  • Digital Electronics : Number Systems, Boolean Algebra
  • Introduction to Embedded System , ESDLC
  • Operational Amplifiers
  • Combinational and Sequential logic
  • Processor Characteristics, Memory devices and hierarchy
  • Network Theory
  • Implementation of Circuits
  • IO devices and methods, Bus Characteristics

Programming in C and Data Structures - 24 days

  • Introduction to C, C Standards
  • Preprocessor Directives
  • Pointers
  • File I/O : Sequential and Random Access
  • Function Pointers
  • Command Line Arguments
  • Decision control statements & Loops
  • Storage classes
  • Dynamic Memory
  • Data structures : Stacks, Queues , Link lists
  • Variable number of arguments
  • Formatted I/O
  • Modular programming using functions
  • Arrays and Strings
  • User Defined Data Types
  • Binary Trees & Expression Trees
  • Internal Linkage & External Linkage

ARM7 Architecture Programming in Embedded C & Embedded Protocols - 14 days

  • Introduction to ARM7
  • Vector Interrupt Controller and Timers
  • Introduction to ARM Cortex M4
  • Introduction to LPC2129
  • ADC, PWM,WDT,RTC
  • GPIO
  • Embedded Protocols - UART, I2C, SPI

Linux Commands & Shell Scripting - 5 days

  • File & Directory Commands Ls, mkdir, cd, pwd, rm,cat
  • Shell Scripting
  • Process Related Commands Ps, fg, bg, jobs
  • Conditions: if, switch, expr, test
  • Text Manipulation Commands Head, tail, cut, paste, sort, diff, comm
  • Loops: while, for

Part II - VLSI Design Specialization

Advance Digital System Design - 12 days

  • Introduction to Digital system
  • Logic gates, Digital logic families
  • Synchronous FSM Design
  • Number Systems, Boolean Expressions
  • combinational & Sequential circuits Design
  • Introduction to HDL, Design Capture and Simulation
  • Simplification techniques, K-maps
  • Registers and Counters Design
  • Digital System Design examples – Hands on

Verilog/VHDL Programming - 15 days

  • Introduction to Verilog Programming
  • Tasks and Functions and directives
  • Memory modeling and FSM
  • Hardware Modeling
  • Design of Test Benches
  • Introduction VHDL

FPGA Design - Advanced - 8 days

  • Introduction FPGA
  • Constraints, Timing analysis, Area Constraints
  • Introduction To Programmable Logic Devices (PLD), Look Up Tables(LUT)
  • FPGA Debugging and Advanced FPGA: Reset circuits, IP cores, Bus architecture and Protocols
  • FPGA Vendors and Tools: Xilinx Design Flow, Xilinx ISE , Vivado
  • Static Timing Analysis – Global Timing Constraints, Path specific timing constraints, Achieving Timing Closure

HDL Synthesis - 5 days

  • Architecting Speed- throughput, latency, timing analysis
  • Coding for Synthesis-Decision Trees, Design Organization
  • Architecting Area, Power, Static Timing Analysis
  • Floorplanning & Place and Route Optimization-Critical-Path Floorplanning, Relationship between Placement and Routing, I/O Registers
  • Advance Simulations-Testbench Architecture, System Stimulus, Gate-Level Simulations
  • Examples-hands on

System Verilog - 5 days

  • Introduction
  • Constant Class Members
  • Objects and its methods, Constructors
  • Inheritance and subclasses
  • Static Class - Members, Methods
  • Data hiding and encapsulation, Virtual Classes

Functional Verification with SystemVerilog and UVM - 15 days

  • Verification environment and its components, SystemVerilog for Verification - SystemVerilog Event Ordering, Clocking block and Program block
  • OOP's Concept of SystemVerilog - Parameterized classes, Virtual interface, Constrained Randomization techniques, Functional Coverage (Coverage Driven Verification), SystemVerilog Assertions
  • Introduction to UVM, UVM Classes, Sequence Item, Sequencer, Virtual Sequences, Transaction Level Modeling ,UVM Reporting Methods

Projects:

  • Design/Implementation in Wireless Communication Domain
  • Image Processing
  • Digital Signal Processing
  • Networking