Internship in VLSI Design

Eligibility: BE, B.Tech, ME, M.Tech

Intermediate

Overview

Introducing Internship Program on VLSI Design

Description

Cranes Varsity is excited to unveil its 4-week VLSI Design Internship Program, tailored for aspiring engineers seeking hands-on experience in the field of VLSI.

The VLSI Design Internship Program spans four weeks, providing participants with comprehensive knowledge and practical skills in digital circuitry, VLSI design, digital logic, circuit design, and verification methodologies. Through a blend of theoretical sessions, lab exercises, and real-world projects, interns will develop a strong foundation in VLSI technologies. Under the guidance of experienced mentors, interns will work on cutting-edge VLSI projects, gaining expertise in areas such as RTL coding using verilog, synthesis, FPGA design, and verification using System Verilog. This practical experience will enhance their problem-solving abilities, critical thinking, and teamwork skills.

Cranes Varsity believes in a holistic learning approach, and interns will have access to mentoring sessions, industry interactions, and workshops, enriching their overall experience and providing valuable insights into the industry trends and best practices.

The VLSI Design Internship Program is open to students pursuing engineering in electronics, electrical, or related disciplines. A basic understanding of digital logic and familiarity with hardware description languages like Verilog or VHDL will be advantageous.

By participating in this 4-week internship, students will gain a competitive edge in the VLSI job market, equipped with both theoretical knowledge and practical experience. Cranes Varsity has a strong reputation for producing industry-ready professionals, further reinforcing the value of this program. Cranes Varsity has a proven track record of producing industry-ready professionals, further reinforcing the value of this program.

VLSI Internship Program ensures that a fresher is prepared on the entire essential aspects of the VLSI front end domain, including training on VLSI flow, SOC design, verification concepts, digital design, Verilog, and System Verilog. The VLSI design course content is well structured and mapped with leading industry requirements and their standards.

Lack of fundamentals in Advanced Digital Design, Analog Design and Verilog based design and verification becomes a major deterrent for freshers in finding the right career opportunities. VLSI Design Course ensures that freshers are empowered with all the essential skill sets required for various jobs in the VLSI front end domain. The course is completely practical oriented, with each aspect of the course involving multiple hands-on projects.

Course Objectives

Benefits of this program

  • Internship with AICTE Registered company
  • Concept to Project experience
  • Exposure to real time scenarios and challenges
  • Certificate of Participation
  • Have strong fundamentals in HDL
  • Gain exposure to industry standard FPGA Implementation
  • Understanding Different Coding Methodologies
  • To gain an Understanding of RTL coding for synthesis
  • Write Verilog test fixtures for simulation

Tools and Resources

  • Lattice Diamond Tool

Course Content (Syllabus)

Brush Up on Digital Electronics

  • Counter design
  • Design of digital circuits for given concepts

Introduction to VLSI

  • Design Flow of IC
  • HDL
  • Basic concept of Verilog
  • Design Block
  • Stimulus block

Levels of Modeling

  • Switch Level
  • Gate Level

Levels of Modeling

  • Data flow
  • Behavioral

Implementation of Circuit using Verilog

  • Combinational Circuits(Switch Level, Gate Level, Data flow, Behavioral level modeling)
  • Sequential Circuits (Gate Level, Data flow, Behavioral level modeling)

Design of Test Bench

  • Introduction To TestBench
  • Implementation of     test     benches     for combinational circuits
  • Implementation of     test     benches     for sequential circuits

Implementation of Counter using Verilog

  • Up Counter
  • Down counter
  • Updown counter

Implementation of Counter using Verilog

  • Johnson counter
  • Ring counter
  • Excess 3 counter

Implementation of Shift register using Verilog

  • SISO
  • SIPO
  • PISO
  • PIPO

Implementation of Shift register using Verilog

  • Arithmetic Shift operator usage for shift operation in Verilog HDL

Implementation of Circuit using Verilog

  • ALU
  • MAC unit

Design of FSM using Verilog

  • Mealy Machine

Design of FSM using Verilog

  • Moore Machine

Memory Modeling

  • Design of Memory using RTL coding
    • RAM Design(single and dual port)
    • ROM Design

Timer

  • Introduction to Timer
  • Implementation of timer using Verilog HDL

PWM

  • Introduction to PWM
  • Implementation of PWM using Verilog HDL

Frequency divider

  • Introduction frequency divider
  • Implementation of frequency divider using Verilog HDL

Design of FIFO

  • Introduction to FIFO
  • Implementation of FIFO using Verilog HDL

DesignofProtocols:

UART

  • IntroductiontoUART
  • Baudratecalculation
  • AdvantagesanddisadvantagesofUART
  • DesignofUARTusingVerilogHDL

SPI

  • IntroductiontoSPI
  • Advantagesanddisadvantages ofUART
  • DesignofSPIusingVerilogHDL

 

Projects

Design of Protocols:

UART

  • Introduction to UART
  • Baud rate calculation
  • Advantages and disadvantages of UART
  • Design of UART using Verilog HDL

SPI

  • Introduction to SPI
  • Advantages and disadvantages of UART
  • Design of SPI using Verilog HDL

Placement Statistics

FAQs

Yes, Cranes Varsity training is available through online

 

Our Online training is Instructor-Led live online sessions

Yes, we will provide training course material for each module

Yes, we offer weekend classes as well evening classes.

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