Internship in VLSI Design & Verification

Eligibility: BE, B.Tech, ME, M.Tech



VLSI Internship


VLSI Design Course with Placement ensures that a fresher is prepared on the entire essential aspects of the VLSI front end domain, including training on VLSI flow, SOC design, verification concepts, digital design, Verilog, and System Verilog. The VLSI design course content is well structured and mapped with leading industry requirements and their standards.

Lack of fundamentals in Advanced Digital Design, Analog Design and Verilog based design and verification becomes a major deterrent for freshers in finding the right career opportunities. VLSI Design Course ensures that freshers are empowered with all the essential skill sets required for various jobs in the VLSI front end domain. The course is completely practical oriented, with each aspect of the course involving multiple hands-on projects.

VLSI Design

  • Foundation to Basic Electronics concepts
  • Programming In C
  • Linux Commands and Shell scripting
  • Introduction to VLSI Basic Verilog and Advanced Verilog
  • FPGA Design Basic and Advance System Verilog
  • UVM(Universal Verification Method)
  • OVM Methodology
  • Project with lattice board – UART / 12C / SPI


  • Lattice Diamond Tool
  • Lattice Eval Boards


  • Introduction to C
  • Data types
  • Operators
  • Control Flow
  • Modular Programming Preprocessor
  • Storage classes
  • Arrays & Strings – Character Arrays
  • Advanced C Programming and more

  • Introduction to object oriented programming
  • Constructor and Destructor
  • Generic Programming
  • Exception handling
  • Procedural approach in C++
  • Copy Constructors
  • Generalization
  • C++14 Library Features and more..

  • Designing Methodology
  • Verilog data types
  • Gate Instantiate
  • Top Down Methodology
  • Loop: While, do while, for, for each, forever, repeat.
  • Block statement, Sequential block, parallel Block, and more..

  • Introduction to FPGA
  • CPLD, FPGA, FPGA Working, Design Flow
  • Design and Implementation of projects on FPGA
  • FPGA Architecture
  • Interconnects, Tool Installation
  • CLB, I/O blocks
  • UART, SPI, FPGA AURDINO interfacing, and more..

  • Introduction of System Verilog , Need of system verilog
  • Array- Fixed array- packed and unpackled array
  • Process:- Fork-join, Fork-join any, Fork-join none, Wait-fork
  • Environment of Verification
  • Dynamic Array, Associative array
  • Queues
  • Working on verification environment and more..

  • Introduction UVM: why UVM
  • Analysis, Fifo, UVM socket concept, working on digital circuit
  • Data Introduction UVM: why UVM UVM Object: Base class
  • UVM object-Copy/Clone types -2satete
  • UVM test Bench

  • Introduction OVM
  • OVM  Sequence 1: Introduction, example, sequencer, divider
  • OVM Reporting
  • OVM Sequence 2: Sequence action macro, list of sequence action macros
  • OVM Transaction
  • OVM Configuration

Projects with Lattice boards on UART / I2C/ SPI


  • Design and implementation of protocols such as UART, SPI, I2C on Lattice FPGA Board
  • Design and implementation of VGA on Lattice FPGA Board

Placement Statistics


Yes, Cranes Varsity training is available through online


Our Online training is Instructor-Led live online sessions

Yes, we will provide training course material for each module

Yes, we offer weekend classes as well evening classes.



Duration: 5 months
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