Internship in VLSI Design & Verification

Eligibility: BE, B.Tech, ME, M.Tech

Intermediate

Overview

VLSI Internship

Description

VLSI Internship Program ensures that a fresher is prepared on the entire essential aspects of the VLSI front end domain, including training on VLSI flow, SOC design, verification concepts, digital design, Verilog, and System Verilog. The VLSI design course content is well structured and mapped with leading industry requirements and their standards.

Lack of fundamentals in Advanced Digital Design, Analog Design and Verilog based design and verification becomes a major deterrent for freshers in finding the right career opportunities. VLSI Design Course ensures that freshers are empowered with all the essential skill sets required for various jobs in the VLSI front end domain. The course is completely practical oriented, with each aspect of the course involving multiple hands-on projects.

Course Objectives

  • Have strong fundamentals in HDL
  • Gain exposure to industry standard FPGA Implementation
  • Understanding Different Coding Methodologies
  • To gain an Understanding of RTL coding for synthesis
  • Write Verilog test fixtures for simulation

Tools and Resources

  • Lattice Diamond Tool

Course Content (Syllabus)

  • Counter design
  • Design of digital circuits for given concepts

  • Design Flow of IC
  • HDL
  • Basic concept of Verilog
  • Design Block
  • Stimulus block

  • Switch Level
  • Gate Level

  • Data flow
  • Behavioral

  • Combinational Circuits(Switch Level, Gate Level, Data flow, Behavioral level modeling)
  • Sequential Circuits (Gate Level, Data flow, Behavioral level modeling)

  • Introduction To TestBench
  • Implementation of     test     benches     for combinational circuits
  • Implementation of     test     benches     for sequential circuits

  • Up Counter
  • Down counter
  • Updown counter

  • Johnson counter
  • Ring counter
  • Excess 3 counter

  • Arithmetic Shift operator usage for shift operation in Verilog HDL

  • Design of Memory using RTL coding
    • RAM Design(single and dual port)
    • ROM Design

  • Introduction to Timer
  • Implementation of timer using Verilog HDL

  • Introduction to PWM
  • Implementation of PWM using Verilog HDL

  • Introduction frequency divider
  • Implementation of frequency divider using Verilog HDL

  • Introduction to FIFO
  • Implementation of FIFO using Verilog HDL

 

Projects

Design of Protocols:

UART

  • Introduction to UART
  • Baud rate calculation
  • Advantages and disadvantages of UART
  • Design of UART using Verilog HDL

SPI

  • Introduction to SPI
  • Advantages and disadvantages of UART
  • Design of SPI using Verilog HDL

Placement Statistics

FAQs

Yes, Cranes Varsity training is available through online

 

Our Online training is Instructor-Led live online sessions

Yes, we will provide training course material for each module

Yes, we offer weekend classes as well evening classes.

Testimonials

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Duration: 1 month / 6 months
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