Internship in VLSI Design & Verification

Eligibility: BE, B.Tech, ME, M.Tech

Intermediate

Overview

VLSI Internship

Description

VLSI Internship Program ensures that a fresher is prepared on the entire essential aspects of the VLSI front end domain, including training on VLSI flow, SOC design, verification concepts, digital design, Verilog, and System Verilog. The VLSI design course content is well structured and mapped with leading industry requirements and their standards.

Lack of fundamentals in Advanced Digital Design, Analog Design and Verilog based design and verification becomes a major deterrent for freshers in finding the right career opportunities. VLSI Design Course ensures that freshers are empowered with all the essential skill sets required for various jobs in the VLSI front end domain. The course is completely practical oriented, with each aspect of the course involving multiple hands-on projects.

VLSI Internship Course Content

  • Foundation to Basic Electronics concepts
  • Programming In C
  • Linux Commands and Shell scripting
  • Introduction to VLSI Basic Verilog and Advanced Verilog
  • FPGA Design Basic and Advance System Verilog
  • UVM(Universal Verification Method)
  • OVM Methodology
  • Project with lattice board – UART / 12C / SPI

Platform

  • Lattice Diamond Tool
  • Lattice Eval Boards

VLSI Internship Course Syllabus

  • Introduction to C
  • Data types
  • Operators
  • Control Flow
  • Modular Programming
  • Preprocessor
  • Storage classes
  • Arrays & Strings – Character Arrays
  • Advanced C Programming:Pointers
  • Advanced Pointers: NULL pointer
  • Dynamic memory allocation
  • Recursion
  • Pointer to a constant, constant pointer
  • Stack and Queues
  • Linked list introduction
  • Introduction Data structures
  • Trees Introduction
  • BST and Expressions
  • Linked List

  • Introduction to object oriented programming
  • Procedural approach in C++
  • Object-oriented approach in C++
  • Constructor and Destructor
  • Copy Constructors
  • Friends and operators overloading
  • Generic Programming
  • Generalization
  • Runtime polymorphism
  • Exception handling
  • C++14 Library Features

  • Designing Methodology
  • Top Down Methodology
  • Bottom Up Methodology
  • Verilog data types
  • Verilog Scalar /Vector
  • Verilog Arrays
  • GATE LEVEL MODELING
  • Gate Instantiate
  • Design RTL From logic Diagram
  • Logic Gate primitive
  • Delay in Gate level Design
  • Learning about different types of the counter, register
  • Data Flow modeling
  • Continuous Assignment’s statement
  • Synchronous Finite State Machine Design.
  • BEHAVIORAL MODELING
  • Structured procedural Statement: Always Statement, Procedural Statement
  • Blocking Statement, Non-Blocking statement
  • Timing Control Statement: Delay based timing control, Event Based timing control
  • Conditional Statement: If. Else statement, case statement: casex, casez
  • Loop: While, do while, for , for each, forever, repeat.
  • Block statement, Sequential block, parallel Block
  • DESIGN OF DIGITAL DEVICES:
  • FSM: Mealy machine, Moore machine
  • Flip flop, Counters, PWM
  • Useful of Modeling Technique
  • All combinational and sequential circuit using Verilog
  • Delay Control Statement:  Intra delay, inter delay, rise delay, fall delay
  • Procedural continuous, Assignment Statement
  • Deassign Statement, force statement, Release statement
  • CRC checking, UART

  • Introduction to FPGA
  • FPGA Architecture
  • CLB, I/O blocks
  • CPLD, FPGA, FPGA Working, Design Flow
  • Interconnects, Tool Installation
  • Working Designing basic FPGS example (Adder, Subtractor, Counter)
  • Design and Implementation of projects on FPGA
  • Implementation of Counter – up counter, down counter, up down counter, mod counter, Johnson counter, ring counter
  • UART, SPI

  • Introduction of System Verilog , Need of system verilog
  • Environment of Verification
  • Data types -2satete, 4 state, enum  string, structure, union, class
  • Array- Fixed array- packed and unpackled array
  • Dynamic Array, Associative array
  • Queues
  • Process:- Fork-join, Fork-join any, Fork-join none, Wait-fork
  • OOPS- Inheritance, Polymorphism, Data hiding, Encapsulation
  • Class- Deep copy, shallow copy, Overriding class, Coverage: Functional Coverage, Cross coverage
  • Queues
  • Explanation of assertion with example
  • Explanation of coverage with example
  • Working on verification environment

  • Introduction UVM: UVM Objects and Macros
  • UVM components, Factory, Phases, Message Reporting, UVM config_db
  • TLM Ports
  • UVM Callbacks
  • UVM test Bench’s

Projects with Lattice boards on UART / I2C/ SPI

Syllabus

  • Design and implementation of protocols such as UART, SPI, I2C on Lattice FPGA Board
  • Design and implementation of VGA on Lattice FPGA Board

Placement Statistics

FAQs

Yes, Cranes Varsity training is available through online

 

Our Online training is Instructor-Led live online sessions

Yes, we will provide training course material for each module

Yes, we offer weekend classes as well evening classes.

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Duration: 5 months
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