Digital Logic Design with Verilog HDL

Eligibility: Working Professional/ Individual/ B.tech, M.tech students
Duration: 1 Month

Contact for Training

Modules

  • Introduction
  • Levels of Modeling
  • Implementation of Circuit using Verilog
  • Design of FSM using Verilog
  • Memory Modeling
  • Design of Test Bench
  • Project

Introduction

  • Design Flow of IC
  • HDL
  • Basic concept of Verilog HDL
  • Design Block
  • Stimulus block

Levels of Modeling

  • Switch Level
  • Gate Level
  • Data flow
  • Behavioral

Implementation of Circuit using Verilog

  • Combinational Circuits(Switch Level, Gate Level, Data flow, Behavioral level modeling)
  • Sequential Circuits (Gate Level, Data flow, Behavioral level modeling)
  • Counter, SISO, SIPO, PISO, PIPO, ALU, MAC unit

Design of FSM using Verilog

  • Mealy Machine
  • Moore Machine

Memory Modeling

  • Design of Memory using RTL coding
  • RAM Design(single and dual port)
  • ROM Design

Design of Test Bench

  • Introduction To Test Bench
  • Introduction to Test benches
  • Implementation of test benches for combinational circuits
  • Implementation of test benches for sequential circuits

Project

  • Design of Protocol
  • UART
  • Design of FIFO