PG Diploma in VLSI Design & ASIC Verification
100% JOB Assured with Globally Accepted Certificate
Duration: 6 Months
Eligibility: BE, B.Tech, ME, M.Tech
Intermediate
Modules
Core Engineering – 40 hrs.
- Digital Hardware Familiarization
- Digital Electronics and Logical Circuit Design
- Timing Analysis
- Mastering OOP using C++
- Linux Basic Commands
- RTL Coding with Verilog
- Digital Circuit Design using different Modeling Styles
- On-Chip Protocol Design
- FPGA Programming
- Prototype Digital System Design using RTL Modeling,
- FPGA Deployment, and SystemVerilog-Based Verification
SPECIALIZATIONS:
- Design and Verification using System Verilog – 100 hrs.
- OOPs in System Verilog
- Randomization & Constraints
- Functional Coverage
- Test bench development
- Duration Break up:
- Training – 55 Days (Excluding DHF)
- Project & Assessment & Technical Mock – 10 Days
Project stream:
- Core Programming
- Application development based on Data Structure (e.g., Multi Client Chat Application, Memory Leak Detection Toolkit, E-Commerce Cart Simulator)
- VLSI
- Design and Simulation of Digital Controller / CPU Core / Protocols such as UART, SPI, I2C, AXI4
- Design, Simulation, Implementation, and Verification of Digital Controllers, ALU Cores, and Protocols such as UART, SPI, I2C, AXI4 on FPGA Board
- SystemVerilog Verification of Digital Controller / CPU Core / Protocols such as UART, SPI, I2C, AXI4
Platform:
- XILINX VIVADO
- Questasim / EDA Playground
- Artix-7 FPGA Board / ZYNQ SoC Board
| Core Engineering | ||
|---|---|---|
| Digital Hardware Familiarization – 40 hrs. – 10 Days – 2 weeks | ||
| Analog Electronics: Ohm’s Law, RC Circuits, Power Supply Basics | Diodes, Rectifiers, Zener & Clamping Circuits | BJTs and MOSFETs (Switching & Amplification |
| Operational Amplifiers (Op-Amps), Filters, Comparators | Digital Electronics & Logic Design: Number Systems & Boolean Algebra | Logic Gates, Multiplexers, Encoders/Decoders |
| Flip-Flops, Counters, Shift Registers, | FSMs | Timing Analysis |
| Core Programming Fundamentals | ||
|---|---|---|
| Mastering OOP using C++ & Competitive problem solving – 60 hrs. – 15 Days – 3 weeks | ||
| Master in C Programming: Simple C program structure | Literals, Constants, | Variables and Data types |
| Arrays | Sorting and searching | Strings |
| Mastering in C++ with OOPs concepts: Introduction to Object-Oriented Programming | Understanding OOP concepts | Objects |
| Understanding namespace | Classes | Basic input/output: cin, cout, endl |
| Abstraction | Encapsulation, | Access Specifiers – Private and Protected, |
| This pointer | Constructors and Destructors | Friends and operator overloading |
| This pointer | Constructors and Destructors | Friends and operator overloading |
| Inheritance | Run time polymorphism | Exception Handling |
| Lambda Expression | Smart Pointers Templates | STL Problem Solving using Hacker rank |
| VLSI Design | ||
|---|---|---|
| RTL Coding with Verilog – 60 hrs. – 15 Days – 3 weeks | ||
| INTRODUCTION TO VLSI: Fundamentals of VLSI | Design Methodology | Verilog data types, Verilog Operators |
| GATE LEVEL MODELING: Gate Instantiate | Design RTL From logic Diagram, Logic Gate primitive | Delay in Gate level Design |
| DATA FLOW MODELING: Operators in Data Flow | Continuous Assignment (assign statement) | Boolean Equations Representation |
| Gate-level Abstraction using Data Flow | Conditional Assignment (Ternary Operator? | Procedural continuous Assignment Statement |
| Procedural vs Continuous Assignment | Parameterized Data Flow Design Delay Modeling in Data Flow | Case Studies / Examples (ALU, Adders, MUX, Encoders) |
| BEHAVIORAL MODELING: Structured procedural Statement: Always Statement, Procedural Statement | Blocking Statement, Non-Blocking statement | Timing Control Statement: Delay based timing control; Event Based timing control |
| Conditional Statement: If else statement, case statement: casex, casez | Loop: While, do while, for, for each, forever, repeat. | Block statement; Sequential block, Parallel Block |
| De-assign Statement, force statement, Release statement | DESIGN OF DIGITAL CIRCUITS: FSM: Mealy machine, Moore machine | Flip-flops |
| Counters, Shift Registers | All combinational and sequential circuits using Verilog | CRC checking, PWM |
| DESIGN OF DIGITAL CIRCUITS: FSM: Mealy machine, Moore machine | Flip-flops | Counters, Shift Registers |
| Useful of Modeling Technique | All combinational and sequential circuit using Verilog | Delay Control Statement: Intra delay, inter delay, rise delay, fall delay |
| Procedural continuous, Assignment Statement | De-assign Statement, force statement, Release statement | CRC checking, PWM |
| On-Chip Protocols Design – 20 hrs. – 5 Days – 1 weeks | ||
| UART (Universal Asynchronous Receiver Transmitter) protocol | SPI (Serial Peripheral Interface) protocol | I2C (Inter Integrated Circuit) protocol |
| AXI4 (Advanced extensible Interface 4) protocol | ||
| FPGA Programming – 40 hrs. – 10 Days – 2 weeks | ||
|---|---|---|
| Introduction to FPGA | FPGA Architecture | CLB, I/O blocks, Interconnects |
| CPLD, FPGA, FPGA Working, | Design Flow, Tool Understanding | working Designing basic FPGS example (Adders, Subtractors, Counter) |
| Implementation of all the combinational circuits on FPGA | Implementation of Flip-flops on FPGA | Implementation of Counters- up counter, down counter, up-down counter, modcounter, Johnson counter, ring counter |
| Realization of Shift Registersv | Realization of FSM: Mealy machine, Moore machine, Designing with VIO and ILA | Demonstration of a Project on FPGA |
| Experiential Project based learning | ||
| Project: Digital design innovators: RTL to realization | ||
| Specializations | ||
|---|---|---|
| VLSI Verification using System Verilog | ||
| Design and Verification using System Verilog – 100 hrs. – 25 Days – 5 weeks | ||
| Introduction of System Verilog, Need of system Verilog | Environment of Verification | Data types-2satete, 4 state, enum ,string, structure, union, class |
| Array- Fixed array- packed and unpacked array | Dynamic Array, Associative array | Queues |
| Process: - Fork-join, Fork-join any, Fork- join none, Wait-fork | OOPS-Inheritance, Polymorphism, Data hiding, Encapsulation | Class- Deep copy, shallow copy,Overriding class, Coverage: Functional Coverage, Cross coverage. |
| Explanation of assertion with example | Explanation of coverage with example | Working on verification environment |
| ASIC Verification using UVM | ||
| Verification using UVM (Universal Verification Methodology) – 60 hrs. – 15 Days – 3 weeks | ||
| Introduction UVM: why UVM | UVM Objects: Base classes | UVM Macros, UVM Base Class Methods |
| UVM Phases, UVM Config DB, UVM Reporting Mechanism | UVM TLM Ports, Analysis, FIFO, UVM socket concept, UVM Callbacks | UVM test Bench Components and UVM test Benches. |
| On-Chip Protocols Verification – 20 hrs. – 5 Days – 1 weeks | ||
| UART (Universal Asynchronous Receiver Transmitter) protocol | SPI (Serial Peripheral Interface) protocol | I2C (Inter Integrated Circuit) protocol |
| AXI4 (Advanced eXtensible Interface 4)protocol | ||
| Experiential Project based learning | ||
| Project: Functional Verification: System Verilog to UVM | ||
| Python Scripting – 40 hrs. – 10 Days – 2 weeks | ||
| Python Fundamentals for Engineers | Data Structures and File Handling | Regular Expressions & Pattern Matching |
| Scripting for EDA Automation | Parsing Reports & Timing Files | Visualization & Reporting |
| Python for Verification & Testbenches | ||
| Timing Verification | ||
| Static Timing Analysis – 40 hrs. – 10 Days – 2 weeks | ||
| Introduction to RTL Linting and CDC | Introduction RTL Synthesis flow | Clocking and Clock domain/synchronization concepts |
| Timing Constraints Overview | Writing constraints | Submicron Process nodes and Technology libraries understanding |
| Synthesis process | Design optimization and netlist generation | Logic equivalence (LEC) /formality verification |
| Introduction to Static Timing Analysis,Terminologies in STA | Timing Fundamentals - Clock, reset,delays | Timing checks, Setup, Hold,Metastability etc |
| Understanding Timing Paths and types of timing paths | Timing checks | Timing Analysis for Combinational &Sequential Logic Circuits |
| Static Timing Analysis (STA) Flow understanding | Inputs and outputs of STA | Design rule violations |
| Timing exceptions | PVT corners and OCV | Understanding Setup and Usage of EDA tools relevant for Syntheis and STA |
Downloads
FAQs
Who is eligible to enroll in this course?
The course is designed for:
- Engineering graduates in Electronics, Electrical, and Circuit branch students.
- Individuals with a foundational understanding of digital electronics and programming.
Is prior programming experience required?
Yes, a basic understanding of programming concepts is beneficial. Familiarity with hardware description languages like Verilog or SystemVerilog is advantageous but not mandatory.
What topics are covered in the curriculum?
The program includes comprehensive modules on:
- Digital Design: Verilog, SystemVerilog
- Verification Techniques: UVM, SV
- Protocol Verification: UART, I2C, SPI, AXI4
- FPGA Implementation: Hands-on with Artix boards
- Design Methodologies: RTL design, synthesis, and timing analysis
What tools and software are used during the training?
Students gain practical experience with industry-standard Electronic Design Automation (EDA) tools, including:
- Cadence: For schematic capture and layout
- Synopsys: For synthesis and simulation
- Mentor Graphics: For PCB design and verification
- ModelSim: For simulation of HDL designs
Is the course available online?
Yes, Cranes Varsity offers live instructor-led online sessions, allowing flexibility for remote learning.
What is the certification provided upon completion?
Upon successful completion, students receive a Postgraduate Diploma Certificate from Cranes Varsity, recognized within the industry.
Does Cranes Varsity offer placement assistance?
Yes, Cranes Varsity provides 100% job assistance, leveraging partnerships with over 500 hiring companies. Placement support includes:
- Resume preparation
- Mock interviews
- Access to job opportunities in VLSI design, verification, and related fields
What are the prerequisites for enrolling in the VLSI course?
Ideal candidates should have:
- A Bachelor’s degree in Electronics, Electrical Engineering, Computer Science, or related fields
- A basic understanding of digital and analog electronics
- Familiarity with HDLs is advantageous but not mandatory for beginners
What job roles can I pursue after completing the VLSI course?
Graduates can explore various roles, such as:
- VLSI Design Engineer
- Verification Engineer
- RTL Design Engineer
- ASIC Designer
- FPGA Designer
- Embedded Systems Engineer with a focus on hardware
How can I enroll in the VLSI course at Cranes Varsity?
To enroll:
- Online: Fill out the application form on the official website, and a dedicated admission counselor will contact you.
- Offline: Visit the Cranes Varsity campus for direct inquiries and enrollment assistance.
What is the fee structure for the VLSI course?
The exact fee details are not publicly listed. For information on course fees and available scholarships, please contact Cranes Varsity directly.
Are there any scholarships or financial aid options available?
Cranes Varsity offers a Scholarship Test. For eligibility criteria, test dates, and details on fee waivers, please reach out to their admissions team.
