POP in VLSI Design & Verification

Eligibility: BE, B.Tech, ME, M.Tech

Intermediate

Overview

VLSI Course with Placement

Description

VLSI Design Course with Placement ensures that a fresher is prepared on the entire essential aspects of the VLSI front end domain, including training on VLSI flow, SOC design, verification concepts, digital design, Verilog, and System Verilog. The VLSI design course content is well structured and mapped with leading industry requirements and their standards.

Lack of fundamentals in Advanced Digital Design, Analog Design and Verilog based design and verification becomes a major deterrent for freshers in finding the right career opportunities. VLSI Design Course ensures that freshers are empowered with all the essential skill sets required for various jobs in the VLSI front end domain. The course is completely practical oriented, with each aspect of the course involving multiple hands-on projects.

VLSI Course Modules

Generic 

  • Foundation to Basic Electronics concepts
  • Programming in C and Data Structures
  • OOPs with C++14
  • Basic Verilog and Advanced Verilog
  • FPGA Design Basic and Advanced
  • System Verilog
  • UVM (Universal Verification Method)

Platform

  • XILINX
  • Modelsim/EDA Playground

Projects Stream

  • Design and Verification of Memory Model using Verilog, System Verilog and UVM.
  • Design and Verification of 32-bit ALU using Verilog, System Verilog and UVM.
  • Design and Verification of UART Protocol using Verilog, System Verilog and UVM.
  • Design and Verification of SPI/I2C Protocol using Verilog, System Verilog and UVM.
  • Design and Verification of FPU using Verilog, System Verilog and­­ UVM.­­­

VLSI Course Content

  • Counter design
  • Design of digital circuits for given concepts

  • Design Flow of IC
  • HDL
  • Basic concept of Verilog
  • Design Block
  • Stimulus block

  • Switch Level
  • Gate Level

  • Data flow
  • Behavioral

  • Combinational Circuits(Switch Level, Gate Level, Data flow, Behavioral level modeling)
  • Sequential Circuits (Gate Level, Data flow, Behavioral level modeling)

  • Introduction To TestBench
  • Implementation of     test     benches     for combinational circuits
  • Implementation of     test     benches     for sequential circuits

  • Up Counter
  • Down counter
  • Updown counter

  • Johnson counter
  • Ring counter
  • Excess 3 counter

  • Arithmetic Shift operator usage for shift operation in Verilog HDL

  • Design of Memory using RTL coding
    • RAM Design(single and dual port)
    • ROM Design

  • Introduction to Timer
  • Implementation of timer using Verilog HDL

  • Introduction to PWM
  • Implementation of PWM using Verilog HDL

  • Introduction frequency divider
  • Implementation of frequency divider using Verilog HDL

  • Introduction to FIFO
  • Implementation of FIFO using Verilog HDL

 

Placement Statistics

FAQs

One should clear the pre-placement process which includes Aptitude tests, Placement tests, and Technical and HR Practice Tests Interviews.  Clearing these tests is mandatory for anyone to get into placements.

Our Principle- “We assist until we place”. Cranes Varsity shoulders the responsibility of placing its students. So anyone who is joining the course at Cranes Varsity is provided with assured placements.

No. Once a student is enrolled in the program, he will get access to our Student Portal which will have study material and interview questions. Cranes Varsity has ATPC – Admission, Training, Placement, and Certificate – Approach. There are no additional charges involved. 

If any student wants to have a hard copy of course material then they may have to bear a nominal charge which is not a part of the regular course fee. 

Testimonials

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Duration: 5 months (At Cranes Varsity) 
240hrs (At College Premises)
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